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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Gowin Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>v1.8.0.02Beta</td>
</tr>
<tr>
<td class="label">Series, Device, Package, Speed, Operating Conditions</td>
<td>GW1N, GW1N-4, LQFP144, 6, COMMERCIAL</td>
</tr>
<tr>
<td class="label">Design Name</td>
<td>demo</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\Gowin\gowin-blink\impl\synthesize\rev_1\fpga_project.vm</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>C:\Gowin\gowin-blink\src\fpga_project.sdc</td>
</tr>
<tr>
<td class="label">Timing Report File</td>
<td>C:\Gowin\gowin-blink\impl\pnr\fpga_project.tr.html</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Mon Oct 08 09:41:57 2018
</td>
</tr>
<tr>
<td class="label">Command Line</td>
<td>C:\Gowin\1.8\Pnr\bin\gowin.exe -do C:\Gowin\gowin-blink\impl\pnr\cmd.do </td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2017 Gowin Semiconductor Corporation.                      All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 1.14V 85C</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 1.26V 0C</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>71</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>495</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>1</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>10</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>DEFAULT_CLK</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Fmax</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>DEFAULT_CLK</td>
<td>119.802(MHz)</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>DEFAULT_CLK</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>DEFAULT_CLK</td>
<td>Hold</td>
<td>-0.397</td>
<td>10</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>1.653</td>
<td>\cnt_Z[22] /Q</td>
<td>\cnt_Z[6] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.747</td>
</tr>
<tr>
<td>2</td>
<td>1.653</td>
<td>\cnt_Z[22] /Q</td>
<td>\cnt_Z[12] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.747</td>
</tr>
<tr>
<td>3</td>
<td>1.653</td>
<td>\cnt_Z[22] /Q</td>
<td>\cnt_Z[13] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.747</td>
</tr>
<tr>
<td>4</td>
<td>1.653</td>
<td>\cnt_Z[22] /Q</td>
<td>\cnt_Z[14] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.747</td>
</tr>
<tr>
<td>5</td>
<td>1.653</td>
<td>\cnt_Z[22] /Q</td>
<td>\cnt_Z[11] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.747</td>
</tr>
<tr>
<td>6</td>
<td>1.653</td>
<td>\cnt_Z[22] /Q</td>
<td>\cnt_Z[16] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.747</td>
</tr>
<tr>
<td>7</td>
<td>1.754</td>
<td>\cnt_Z[22] /Q</td>
<td>\cnt_Z[24] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.646</td>
</tr>
<tr>
<td>8</td>
<td>1.754</td>
<td>\cnt_Z[22] /Q</td>
<td>\cnt_Z[19] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.646</td>
</tr>
<tr>
<td>9</td>
<td>1.754</td>
<td>\cnt_Z[22] /Q</td>
<td>\cnt_Z[18] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.646</td>
</tr>
<tr>
<td>10</td>
<td>1.754</td>
<td>\cnt_Z[22] /Q</td>
<td>\cnt_Z[20] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.646</td>
</tr>
<tr>
<td>11</td>
<td>1.754</td>
<td>\cnt_Z[22] /Q</td>
<td>\cnt_Z[21] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.646</td>
</tr>
<tr>
<td>12</td>
<td>1.754</td>
<td>\cnt_Z[22] /Q</td>
<td>\cnt_Z[22] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.646</td>
</tr>
<tr>
<td>13</td>
<td>2.582</td>
<td>\cnt_Z[22] /Q</td>
<td>clk_led_Z/CE</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.175</td>
</tr>
<tr>
<td>14</td>
<td>4.406</td>
<td>\u_ao_top/u_ao_mem_ctrl/mem_mem_0_0 /DI4</td>
<td>\u_ao_top/u_ao_mem_ctrl/mem_mem_0_0 /DI4</td>
<td>DEFAULT_CLK:[F]</td>
<td>DEFAULT_CLK:[R]</td>
<td>5.000</td>
<td>-3.385</td>
<td>3.736</td>
</tr>
<tr>
<td>15</td>
<td>4.475</td>
<td>\cnt_Z[6] /Q</td>
<td>\cnt_Z[23] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.925</td>
</tr>
<tr>
<td>16</td>
<td>4.817</td>
<td>\cnt_Z[6] /Q</td>
<td>\cnt_Z[17] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.583</td>
</tr>
<tr>
<td>17</td>
<td>4.931</td>
<td>\cnt_Z[6] /Q</td>
<td>\cnt_Z[15] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.469</td>
</tr>
<tr>
<td>18</td>
<td>5.216</td>
<td>\cnt_Z[6] /Q</td>
<td>\cnt_Z[10] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.184</td>
</tr>
<tr>
<td>19</td>
<td>5.273</td>
<td>\cnt_Z[6] /Q</td>
<td>\cnt_Z[9] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.127</td>
</tr>
<tr>
<td>20</td>
<td>5.330</td>
<td>\cnt_Z[6] /Q</td>
<td>\cnt_Z[8] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.070</td>
</tr>
<tr>
<td>21</td>
<td>5.387</td>
<td>\cnt_Z[6] /Q</td>
<td>\cnt_Z[7] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.013</td>
</tr>
<tr>
<td>22</td>
<td>6.824</td>
<td>\cnt_Z[1] /Q</td>
<td>\cnt_Z[5] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.576</td>
</tr>
<tr>
<td>23</td>
<td>6.881</td>
<td>\cnt_Z[1] /Q</td>
<td>\cnt_Z[4] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.519</td>
</tr>
<tr>
<td>24</td>
<td>6.938</td>
<td>\cnt_Z[1] /Q</td>
<td>\cnt_Z[3] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.462</td>
</tr>
<tr>
<td>25</td>
<td>6.995</td>
<td>\cnt_Z[1] /Q</td>
<td>\cnt_Z[2] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.405</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.708</td>
<td>clk_led_Z/Q</td>
<td>clk_led_Z/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>2</td>
<td>0.853</td>
<td>\cnt_Z[8] /Q</td>
<td>\cnt_Z[8] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.853</td>
</tr>
<tr>
<td>3</td>
<td>0.853</td>
<td>\cnt_Z[0] /Q</td>
<td>\cnt_Z[0] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.853</td>
</tr>
<tr>
<td>4</td>
<td>0.853</td>
<td>\cnt_Z[2] /Q</td>
<td>\cnt_Z[2] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.853</td>
</tr>
<tr>
<td>5</td>
<td>1.085</td>
<td>\cnt_Z[23] /Q</td>
<td>\cnt_Z[23] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.085</td>
</tr>
<tr>
<td>6</td>
<td>1.085</td>
<td>\cnt_Z[10] /Q</td>
<td>\cnt_Z[10] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.085</td>
</tr>
<tr>
<td>7</td>
<td>1.085</td>
<td>\cnt_Z[17] /Q</td>
<td>\cnt_Z[17] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.085</td>
</tr>
<tr>
<td>8</td>
<td>1.085</td>
<td>\cnt_Z[4] /Q</td>
<td>\cnt_Z[4] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.085</td>
</tr>
<tr>
<td>9</td>
<td>1.085</td>
<td>\cnt_Z[5] /Q</td>
<td>\cnt_Z[5] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.085</td>
</tr>
<tr>
<td>10</td>
<td>1.088</td>
<td>\cnt_Z[9] /Q</td>
<td>\cnt_Z[9] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.088</td>
</tr>
<tr>
<td>11</td>
<td>1.088</td>
<td>\cnt_Z[1] /Q</td>
<td>\cnt_Z[1] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.088</td>
</tr>
<tr>
<td>12</td>
<td>1.093</td>
<td>\cnt_Z[7] /Q</td>
<td>\cnt_Z[7] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.093</td>
</tr>
<tr>
<td>13</td>
<td>1.093</td>
<td>\cnt_Z[15] /Q</td>
<td>\cnt_Z[15] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.093</td>
</tr>
<tr>
<td>14</td>
<td>1.093</td>
<td>\cnt_Z[3] /Q</td>
<td>\cnt_Z[3] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.093</td>
</tr>
<tr style="color: #FF0000;">
<td>15</td>
<td>-0.079</td>
<td>\u_ao_top/u_ao_mem_ctrl/mem_mem_0_0 /DI4</td>
<td>\u_ao_top/u_ao_mem_ctrl/mem_mem_0_0 /DI4</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>-2.515</td>
<td>2.522</td>
</tr>
<tr>
<td>16</td>
<td>2.486</td>
<td>\cnt_Z[21] /Q</td>
<td>\cnt_Z[21] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>2.486</td>
</tr>
<tr>
<td>17</td>
<td>2.565</td>
<td>\cnt_Z[24] /Q</td>
<td>\cnt_Z[24] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>2.565</td>
</tr>
<tr>
<td>18</td>
<td>2.608</td>
<td>\cnt_Z[19] /Q</td>
<td>\cnt_Z[19] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>2.608</td>
</tr>
<tr>
<td>19</td>
<td>2.657</td>
<td>\cnt_Z[18] /Q</td>
<td>\cnt_Z[18] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>2.657</td>
</tr>
<tr>
<td>20</td>
<td>2.692</td>
<td>\cnt_Z[13] /Q</td>
<td>\cnt_Z[13] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>2.692</td>
</tr>
<tr>
<td>21</td>
<td>2.751</td>
<td>\cnt_Z[8] /Q</td>
<td>\cnt_Z[14] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>2.751</td>
</tr>
<tr>
<td>22</td>
<td>2.889</td>
<td>\cnt_Z[22] /Q</td>
<td>\cnt_Z[22] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>2.889</td>
</tr>
<tr>
<td>23</td>
<td>2.892</td>
<td>\cnt_Z[20] /Q</td>
<td>\cnt_Z[20] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>2.892</td>
</tr>
<tr>
<td>24</td>
<td>2.939</td>
<td>\cnt_Z[16] /Q</td>
<td>\cnt_Z[16] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>2.939</td>
</tr>
<tr>
<td>25</td>
<td>2.994</td>
<td>\cnt_Z[2] /Q</td>
<td>\cnt_Z[6] /D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>2.994</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>\cnt_Z[5] </td>
</tr>
<tr>
<td>2</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>\cnt_Z[3] </td>
</tr>
<tr>
<td>3</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>\cnt_Z[20] </td>
</tr>
<tr>
<td>4</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>\cnt_Z[12] </td>
</tr>
<tr>
<td>5</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>\u_ao_top/internal_reg_start_dly_Z[0] </td>
</tr>
<tr>
<td>6</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>\u_ao_top/internal_reg_start_dly_Z[1] </td>
</tr>
<tr>
<td>7</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>\cnt_Z[13] </td>
</tr>
<tr>
<td>8</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>\u_ao_top/rst_ao_Z </td>
</tr>
<tr>
<td>9</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>\u_ao_top/rst_ao_syn_Z </td>
</tr>
<tr>
<td>10</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>\cnt_Z[0] </td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.653</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.117</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[22] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[6] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>\cnt_Z[22] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C11[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[22] /Q</td>
</tr>
<tr>
<td>5.966</td>
<td>1.138</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td>clk_led4_16_cZ/I2</td>
</tr>
<tr>
<td>6.998</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td style=" background: #97FFFF;">clk_led4_16_cZ/F</td>
</tr>
<tr>
<td>7.802</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td>clk_led4_22_cZ/I3</td>
</tr>
<tr>
<td>8.834</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td style=" background: #97FFFF;">clk_led4_22_cZ/F</td>
</tr>
<tr>
<td>8.840</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[3][A]</td>
<td>clk_led4_cZ/I2</td>
</tr>
<tr>
<td>9.662</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>13</td>
<td>R12C9[3][A]</td>
<td style=" background: #97FFFF;">clk_led4_cZ/F</td>
</tr>
<tr>
<td>11.491</td>
<td>1.829</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>\cnt_3_cZ[6] /I1</td>
</tr>
<tr>
<td>12.117</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[6] /F</td>
</tr>
<tr>
<td>12.117</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td style=" font-weight:bold;">\cnt_Z[6] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>\cnt_Z[6] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[6] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>\cnt_Z[6] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.512, 45.333%; route: 3.777, 48.751%; tC2Q: 0.458, 5.916%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.653</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.117</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[22] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[12] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>\cnt_Z[22] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C11[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[22] /Q</td>
</tr>
<tr>
<td>5.966</td>
<td>1.138</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td>clk_led4_16_cZ/I2</td>
</tr>
<tr>
<td>6.998</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td style=" background: #97FFFF;">clk_led4_16_cZ/F</td>
</tr>
<tr>
<td>7.802</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td>clk_led4_22_cZ/I3</td>
</tr>
<tr>
<td>8.834</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td style=" background: #97FFFF;">clk_led4_22_cZ/F</td>
</tr>
<tr>
<td>8.840</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[3][A]</td>
<td>clk_led4_cZ/I2</td>
</tr>
<tr>
<td>9.662</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>13</td>
<td>R12C9[3][A]</td>
<td style=" background: #97FFFF;">clk_led4_cZ/F</td>
</tr>
<tr>
<td>11.491</td>
<td>1.829</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[0][B]</td>
<td>\cnt_3_cZ[12] /I1</td>
</tr>
<tr>
<td>12.117</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C12[0][B]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[12] /F</td>
</tr>
<tr>
<td>12.117</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[0][B]</td>
<td style=" font-weight:bold;">\cnt_Z[12] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[0][B]</td>
<td>\cnt_Z[12] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[12] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C12[0][B]</td>
<td>\cnt_Z[12] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.512, 45.333%; route: 3.777, 48.751%; tC2Q: 0.458, 5.916%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.653</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.117</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[22] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[13] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>\cnt_Z[22] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C11[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[22] /Q</td>
</tr>
<tr>
<td>5.966</td>
<td>1.138</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td>clk_led4_16_cZ/I2</td>
</tr>
<tr>
<td>6.998</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td style=" background: #97FFFF;">clk_led4_16_cZ/F</td>
</tr>
<tr>
<td>7.802</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td>clk_led4_22_cZ/I3</td>
</tr>
<tr>
<td>8.834</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td style=" background: #97FFFF;">clk_led4_22_cZ/F</td>
</tr>
<tr>
<td>8.840</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[3][A]</td>
<td>clk_led4_cZ/I2</td>
</tr>
<tr>
<td>9.662</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>13</td>
<td>R12C9[3][A]</td>
<td style=" background: #97FFFF;">clk_led4_cZ/F</td>
</tr>
<tr>
<td>11.491</td>
<td>1.829</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[1][B]</td>
<td>\cnt_3_cZ[13] /I1</td>
</tr>
<tr>
<td>12.117</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C12[1][B]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[13] /F</td>
</tr>
<tr>
<td>12.117</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[1][B]</td>
<td style=" font-weight:bold;">\cnt_Z[13] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[1][B]</td>
<td>\cnt_Z[13] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[13] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C12[1][B]</td>
<td>\cnt_Z[13] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.512, 45.333%; route: 3.777, 48.751%; tC2Q: 0.458, 5.916%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.653</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.117</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[22] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[14] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>\cnt_Z[22] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C11[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[22] /Q</td>
</tr>
<tr>
<td>5.966</td>
<td>1.138</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td>clk_led4_16_cZ/I2</td>
</tr>
<tr>
<td>6.998</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td style=" background: #97FFFF;">clk_led4_16_cZ/F</td>
</tr>
<tr>
<td>7.802</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td>clk_led4_22_cZ/I3</td>
</tr>
<tr>
<td>8.834</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td style=" background: #97FFFF;">clk_led4_22_cZ/F</td>
</tr>
<tr>
<td>8.840</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[3][A]</td>
<td>clk_led4_cZ/I2</td>
</tr>
<tr>
<td>9.662</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>13</td>
<td>R12C9[3][A]</td>
<td style=" background: #97FFFF;">clk_led4_cZ/F</td>
</tr>
<tr>
<td>11.491</td>
<td>1.829</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[2][B]</td>
<td>\cnt_3_cZ[14] /I1</td>
</tr>
<tr>
<td>12.117</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C12[2][B]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[14] /F</td>
</tr>
<tr>
<td>12.117</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[2][B]</td>
<td style=" font-weight:bold;">\cnt_Z[14] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[2][B]</td>
<td>\cnt_Z[14] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[14] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C12[2][B]</td>
<td>\cnt_Z[14] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.512, 45.333%; route: 3.777, 48.751%; tC2Q: 0.458, 5.916%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.653</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.117</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[22] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[11] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>\cnt_Z[22] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C11[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[22] /Q</td>
</tr>
<tr>
<td>5.966</td>
<td>1.138</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td>clk_led4_16_cZ/I2</td>
</tr>
<tr>
<td>6.998</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td style=" background: #97FFFF;">clk_led4_16_cZ/F</td>
</tr>
<tr>
<td>7.802</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td>clk_led4_22_cZ/I3</td>
</tr>
<tr>
<td>8.834</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td style=" background: #97FFFF;">clk_led4_22_cZ/F</td>
</tr>
<tr>
<td>8.840</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[3][A]</td>
<td>clk_led4_cZ/I2</td>
</tr>
<tr>
<td>9.662</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>13</td>
<td>R12C9[3][A]</td>
<td style=" background: #97FFFF;">clk_led4_cZ/F</td>
</tr>
<tr>
<td>11.491</td>
<td>1.829</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[1][A]</td>
<td>\cnt_3_cZ[11] /I1</td>
</tr>
<tr>
<td>12.117</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C12[1][A]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[11] /F</td>
</tr>
<tr>
<td>12.117</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[1][A]</td>
<td style=" font-weight:bold;">\cnt_Z[11] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[1][A]</td>
<td>\cnt_Z[11] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[11] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C12[1][A]</td>
<td>\cnt_Z[11] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.512, 45.333%; route: 3.777, 48.751%; tC2Q: 0.458, 5.916%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.653</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.117</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[22] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[16] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>\cnt_Z[22] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C11[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[22] /Q</td>
</tr>
<tr>
<td>5.966</td>
<td>1.138</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td>clk_led4_16_cZ/I2</td>
</tr>
<tr>
<td>6.998</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td style=" background: #97FFFF;">clk_led4_16_cZ/F</td>
</tr>
<tr>
<td>7.802</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td>clk_led4_22_cZ/I3</td>
</tr>
<tr>
<td>8.834</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td style=" background: #97FFFF;">clk_led4_22_cZ/F</td>
</tr>
<tr>
<td>8.840</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[3][A]</td>
<td>clk_led4_cZ/I2</td>
</tr>
<tr>
<td>9.662</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>13</td>
<td>R12C9[3][A]</td>
<td style=" background: #97FFFF;">clk_led4_cZ/F</td>
</tr>
<tr>
<td>11.491</td>
<td>1.829</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[2][A]</td>
<td>\cnt_3_cZ[16] /I1</td>
</tr>
<tr>
<td>12.117</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C12[2][A]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[16] /F</td>
</tr>
<tr>
<td>12.117</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[16] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[2][A]</td>
<td>\cnt_Z[16] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[16] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C12[2][A]</td>
<td>\cnt_Z[16] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.512, 45.333%; route: 3.777, 48.751%; tC2Q: 0.458, 5.916%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.754</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.016</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[22] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[24] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>\cnt_Z[22] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C11[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[22] /Q</td>
</tr>
<tr>
<td>5.966</td>
<td>1.138</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td>clk_led4_16_cZ/I2</td>
</tr>
<tr>
<td>6.998</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td style=" background: #97FFFF;">clk_led4_16_cZ/F</td>
</tr>
<tr>
<td>7.802</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td>clk_led4_22_cZ/I3</td>
</tr>
<tr>
<td>8.834</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td style=" background: #97FFFF;">clk_led4_22_cZ/F</td>
</tr>
<tr>
<td>8.840</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[3][A]</td>
<td>clk_led4_cZ/I2</td>
</tr>
<tr>
<td>9.662</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>13</td>
<td>R12C9[3][A]</td>
<td style=" background: #97FFFF;">clk_led4_cZ/F</td>
</tr>
<tr>
<td>10.984</td>
<td>1.322</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C11[2][B]</td>
<td>\cnt_3_cZ[24] /I1</td>
</tr>
<tr>
<td>12.016</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[2][B]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[24] /F</td>
</tr>
<tr>
<td>12.016</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C11[2][B]</td>
<td style=" font-weight:bold;">\cnt_Z[24] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][B]</td>
<td>\cnt_Z[24] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[24] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C11[2][B]</td>
<td>\cnt_Z[24] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.918, 51.244%; route: 3.269, 42.761%; tC2Q: 0.458, 5.995%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.754</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.016</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[22] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[19] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>\cnt_Z[22] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C11[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[22] /Q</td>
</tr>
<tr>
<td>5.966</td>
<td>1.138</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td>clk_led4_16_cZ/I2</td>
</tr>
<tr>
<td>6.998</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td style=" background: #97FFFF;">clk_led4_16_cZ/F</td>
</tr>
<tr>
<td>7.802</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td>clk_led4_22_cZ/I3</td>
</tr>
<tr>
<td>8.834</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td style=" background: #97FFFF;">clk_led4_22_cZ/F</td>
</tr>
<tr>
<td>8.840</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[3][A]</td>
<td>clk_led4_cZ/I2</td>
</tr>
<tr>
<td>9.662</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>13</td>
<td>R12C9[3][A]</td>
<td style=" background: #97FFFF;">clk_led4_cZ/F</td>
</tr>
<tr>
<td>10.984</td>
<td>1.322</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C11[0][A]</td>
<td>\cnt_3_cZ[19] /I1</td>
</tr>
<tr>
<td>12.016</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[0][A]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[19] /F</td>
</tr>
<tr>
<td>12.016</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C11[0][A]</td>
<td style=" font-weight:bold;">\cnt_Z[19] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[0][A]</td>
<td>\cnt_Z[19] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[19] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C11[0][A]</td>
<td>\cnt_Z[19] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.918, 51.244%; route: 3.269, 42.761%; tC2Q: 0.458, 5.995%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.754</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.016</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[22] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[18] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>\cnt_Z[22] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C11[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[22] /Q</td>
</tr>
<tr>
<td>5.966</td>
<td>1.138</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td>clk_led4_16_cZ/I2</td>
</tr>
<tr>
<td>6.998</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td style=" background: #97FFFF;">clk_led4_16_cZ/F</td>
</tr>
<tr>
<td>7.802</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td>clk_led4_22_cZ/I3</td>
</tr>
<tr>
<td>8.834</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td style=" background: #97FFFF;">clk_led4_22_cZ/F</td>
</tr>
<tr>
<td>8.840</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[3][A]</td>
<td>clk_led4_cZ/I2</td>
</tr>
<tr>
<td>9.662</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>13</td>
<td>R12C9[3][A]</td>
<td style=" background: #97FFFF;">clk_led4_cZ/F</td>
</tr>
<tr>
<td>10.984</td>
<td>1.322</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C11[0][B]</td>
<td>\cnt_3_cZ[18] /I1</td>
</tr>
<tr>
<td>12.016</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[0][B]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[18] /F</td>
</tr>
<tr>
<td>12.016</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C11[0][B]</td>
<td style=" font-weight:bold;">\cnt_Z[18] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[0][B]</td>
<td>\cnt_Z[18] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[18] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C11[0][B]</td>
<td>\cnt_Z[18] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.918, 51.244%; route: 3.269, 42.761%; tC2Q: 0.458, 5.995%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.754</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.016</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[22] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[20] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>\cnt_Z[22] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C11[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[22] /Q</td>
</tr>
<tr>
<td>5.966</td>
<td>1.138</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td>clk_led4_16_cZ/I2</td>
</tr>
<tr>
<td>6.998</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td style=" background: #97FFFF;">clk_led4_16_cZ/F</td>
</tr>
<tr>
<td>7.802</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td>clk_led4_22_cZ/I3</td>
</tr>
<tr>
<td>8.834</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td style=" background: #97FFFF;">clk_led4_22_cZ/F</td>
</tr>
<tr>
<td>8.840</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[3][A]</td>
<td>clk_led4_cZ/I2</td>
</tr>
<tr>
<td>9.662</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>13</td>
<td>R12C9[3][A]</td>
<td style=" background: #97FFFF;">clk_led4_cZ/F</td>
</tr>
<tr>
<td>10.984</td>
<td>1.322</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C11[1][A]</td>
<td>\cnt_3_cZ[20] /I1</td>
</tr>
<tr>
<td>12.016</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[1][A]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[20] /F</td>
</tr>
<tr>
<td>12.016</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C11[1][A]</td>
<td style=" font-weight:bold;">\cnt_Z[20] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[1][A]</td>
<td>\cnt_Z[20] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[20] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C11[1][A]</td>
<td>\cnt_Z[20] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.918, 51.244%; route: 3.269, 42.761%; tC2Q: 0.458, 5.995%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.754</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.016</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[22] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[21] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>\cnt_Z[22] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C11[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[22] /Q</td>
</tr>
<tr>
<td>5.966</td>
<td>1.138</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td>clk_led4_16_cZ/I2</td>
</tr>
<tr>
<td>6.998</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td style=" background: #97FFFF;">clk_led4_16_cZ/F</td>
</tr>
<tr>
<td>7.802</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td>clk_led4_22_cZ/I3</td>
</tr>
<tr>
<td>8.834</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td style=" background: #97FFFF;">clk_led4_22_cZ/F</td>
</tr>
<tr>
<td>8.840</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[3][A]</td>
<td>clk_led4_cZ/I2</td>
</tr>
<tr>
<td>9.662</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>13</td>
<td>R12C9[3][A]</td>
<td style=" background: #97FFFF;">clk_led4_cZ/F</td>
</tr>
<tr>
<td>10.984</td>
<td>1.322</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C11[1][B]</td>
<td>\cnt_3_cZ[21] /I1</td>
</tr>
<tr>
<td>12.016</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[1][B]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[21] /F</td>
</tr>
<tr>
<td>12.016</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C11[1][B]</td>
<td style=" font-weight:bold;">\cnt_Z[21] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[1][B]</td>
<td>\cnt_Z[21] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[21] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C11[1][B]</td>
<td>\cnt_Z[21] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.918, 51.244%; route: 3.269, 42.761%; tC2Q: 0.458, 5.995%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.754</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.016</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[22] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[22] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>\cnt_Z[22] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C11[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[22] /Q</td>
</tr>
<tr>
<td>5.966</td>
<td>1.138</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td>clk_led4_16_cZ/I2</td>
</tr>
<tr>
<td>6.998</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td style=" background: #97FFFF;">clk_led4_16_cZ/F</td>
</tr>
<tr>
<td>7.802</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td>clk_led4_22_cZ/I3</td>
</tr>
<tr>
<td>8.834</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td style=" background: #97FFFF;">clk_led4_22_cZ/F</td>
</tr>
<tr>
<td>8.840</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[3][A]</td>
<td>clk_led4_cZ/I2</td>
</tr>
<tr>
<td>9.662</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>13</td>
<td>R12C9[3][A]</td>
<td style=" background: #97FFFF;">clk_led4_cZ/F</td>
</tr>
<tr>
<td>10.984</td>
<td>1.322</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>\cnt_3_cZ[22] /I1</td>
</tr>
<tr>
<td>12.016</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[22] /F</td>
</tr>
<tr>
<td>12.016</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[22] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>\cnt_Z[22] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[22] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>\cnt_Z[22] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.918, 51.244%; route: 3.269, 42.761%; tC2Q: 0.458, 5.995%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.582</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.544</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.126</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[22] </td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_led_Z</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>\cnt_Z[22] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C11[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[22] /Q</td>
</tr>
<tr>
<td>5.966</td>
<td>1.138</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td>clk_led4_16_cZ/I2</td>
</tr>
<tr>
<td>6.998</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C10[1][A]</td>
<td style=" background: #97FFFF;">clk_led4_16_cZ/F</td>
</tr>
<tr>
<td>7.802</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td>clk_led4_22_cZ/I3</td>
</tr>
<tr>
<td>8.834</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C9[2][A]</td>
<td style=" background: #97FFFF;">clk_led4_22_cZ/F</td>
</tr>
<tr>
<td>8.840</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[3][A]</td>
<td>clk_led4_cZ/I2</td>
</tr>
<tr>
<td>9.642</td>
<td>0.802</td>
<td>tINS</td>
<td>FR</td>
<td>13</td>
<td>R12C9[3][A]</td>
<td style=" background: #97FFFF;">clk_led4_cZ/F</td>
</tr>
<tr>
<td>11.544</td>
<td>1.903</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C9[0][A]</td>
<td style=" font-weight:bold;">clk_led_Z/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C9[0][A]</td>
<td>clk_led_Z/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>clk_led_Z</td>
</tr>
<tr>
<td>14.126</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C9[0][A]</td>
<td>clk_led_Z</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.866, 39.946%; route: 3.850, 53.665%; tC2Q: 0.458, 6.388%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.406</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.720</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.126</td>
</tr>
<tr>
<td class="label">From</td>
<td>\u_ao_top/u_ao_mem_ctrl/mem_mem_0_0 </td>
</tr>
<tr>
<td class="label">To</td>
<td>\u_ao_top/u_ao_mem_ctrl/mem_mem_0_0 </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.720</td>
<td>3.736</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R10[0]</td>
<td style=" font-weight:bold;">\u_ao_top/u_ao_mem_ctrl/mem_mem_0_0 /DI4</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[0]</td>
<td>\u_ao_top/u_ao_mem_ctrl/mem_mem_0_0 /CLKA</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\u_ao_top/u_ao_mem_ctrl/mem_mem_0_0 </td>
</tr>
<tr>
<td>14.126</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R10[0]</td>
<td>\u_ao_top/u_ao_mem_ctrl/mem_mem_0_0 </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>3.385</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>0</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 100.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 3.736, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.475</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.295</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[6] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[23] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>\cnt_Z[6] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C12[0][A]</td>
<td style=" font-weight:bold;">\cnt_Z[6] /Q</td>
</tr>
<tr>
<td>6.775</td>
<td>1.947</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.820</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.820</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>7.877</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/COUT</td>
</tr>
<tr>
<td>7.877</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[1][B]</td>
<td>un3_cnt_cry_8_0/CIN</td>
</tr>
<tr>
<td>7.934</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/COUT</td>
</tr>
<tr>
<td>7.934</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[2][A]</td>
<td>un3_cnt_cry_9_0/CIN</td>
</tr>
<tr>
<td>7.991</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_9_0/COUT</td>
</tr>
<tr>
<td>7.991</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[2][B]</td>
<td>un3_cnt_cry_10_0/CIN</td>
</tr>
<tr>
<td>8.048</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_10_0/COUT</td>
</tr>
<tr>
<td>8.048</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C8[0][A]</td>
<td>un3_cnt_cry_11_0/CIN</td>
</tr>
<tr>
<td>8.105</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C8[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_11_0/COUT</td>
</tr>
<tr>
<td>8.105</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C8[0][B]</td>
<td>un3_cnt_cry_12_0/CIN</td>
</tr>
<tr>
<td>8.162</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C8[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_12_0/COUT</td>
</tr>
<tr>
<td>8.162</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C8[1][A]</td>
<td>un3_cnt_cry_13_0/CIN</td>
</tr>
<tr>
<td>8.219</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C8[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_13_0/COUT</td>
</tr>
<tr>
<td>8.219</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C8[1][B]</td>
<td>un3_cnt_cry_14_0/CIN</td>
</tr>
<tr>
<td>8.276</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C8[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_14_0/COUT</td>
</tr>
<tr>
<td>8.276</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C8[2][A]</td>
<td>un3_cnt_cry_15_0/CIN</td>
</tr>
<tr>
<td>8.333</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C8[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_15_0/COUT</td>
</tr>
<tr>
<td>8.333</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C8[2][B]</td>
<td>un3_cnt_cry_16_0/CIN</td>
</tr>
<tr>
<td>8.390</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C8[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_16_0/COUT</td>
</tr>
<tr>
<td>8.390</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C9[0][A]</td>
<td>un3_cnt_cry_17_0/CIN</td>
</tr>
<tr>
<td>8.447</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C9[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_17_0/COUT</td>
</tr>
<tr>
<td>8.447</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C9[0][B]</td>
<td>un3_cnt_cry_18_0/CIN</td>
</tr>
<tr>
<td>8.504</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C9[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_18_0/COUT</td>
</tr>
<tr>
<td>8.504</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C9[1][A]</td>
<td>un3_cnt_cry_19_0/CIN</td>
</tr>
<tr>
<td>8.561</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C9[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_19_0/COUT</td>
</tr>
<tr>
<td>8.561</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C9[1][B]</td>
<td>un3_cnt_cry_20_0/CIN</td>
</tr>
<tr>
<td>8.618</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C9[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_20_0/COUT</td>
</tr>
<tr>
<td>8.618</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C9[2][A]</td>
<td>un3_cnt_cry_21_0/CIN</td>
</tr>
<tr>
<td>8.675</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C9[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_21_0/COUT</td>
</tr>
<tr>
<td>8.675</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C9[2][B]</td>
<td>un3_cnt_cry_22_0/CIN</td>
</tr>
<tr>
<td>8.732</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C9[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_22_0/COUT</td>
</tr>
<tr>
<td>8.732</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C10[0][A]</td>
<td>un3_cnt_cry_23_0/CIN</td>
</tr>
<tr>
<td>9.295</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C10[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_23_0/SUM</td>
</tr>
<tr>
<td>9.295</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C10[0][A]</td>
<td style=" font-weight:bold;">\cnt_Z[23] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C10[0][A]</td>
<td>\cnt_Z[23] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[23] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C10[0][A]</td>
<td>\cnt_Z[23] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>18</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.520, 51.165%; route: 1.947, 39.529%; tC2Q: 0.458, 9.306%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.817</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.953</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[6] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[17] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>\cnt_Z[6] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C12[0][A]</td>
<td style=" font-weight:bold;">\cnt_Z[6] /Q</td>
</tr>
<tr>
<td>6.775</td>
<td>1.947</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.820</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.820</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>7.877</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/COUT</td>
</tr>
<tr>
<td>7.877</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[1][B]</td>
<td>un3_cnt_cry_8_0/CIN</td>
</tr>
<tr>
<td>7.934</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/COUT</td>
</tr>
<tr>
<td>7.934</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[2][A]</td>
<td>un3_cnt_cry_9_0/CIN</td>
</tr>
<tr>
<td>7.991</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_9_0/COUT</td>
</tr>
<tr>
<td>7.991</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[2][B]</td>
<td>un3_cnt_cry_10_0/CIN</td>
</tr>
<tr>
<td>8.048</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_10_0/COUT</td>
</tr>
<tr>
<td>8.048</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C8[0][A]</td>
<td>un3_cnt_cry_11_0/CIN</td>
</tr>
<tr>
<td>8.105</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C8[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_11_0/COUT</td>
</tr>
<tr>
<td>8.105</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C8[0][B]</td>
<td>un3_cnt_cry_12_0/CIN</td>
</tr>
<tr>
<td>8.162</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C8[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_12_0/COUT</td>
</tr>
<tr>
<td>8.162</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C8[1][A]</td>
<td>un3_cnt_cry_13_0/CIN</td>
</tr>
<tr>
<td>8.219</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C8[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_13_0/COUT</td>
</tr>
<tr>
<td>8.219</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C8[1][B]</td>
<td>un3_cnt_cry_14_0/CIN</td>
</tr>
<tr>
<td>8.276</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C8[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_14_0/COUT</td>
</tr>
<tr>
<td>8.276</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C8[2][A]</td>
<td>un3_cnt_cry_15_0/CIN</td>
</tr>
<tr>
<td>8.333</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C8[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_15_0/COUT</td>
</tr>
<tr>
<td>8.333</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C8[2][B]</td>
<td>un3_cnt_cry_16_0/CIN</td>
</tr>
<tr>
<td>8.390</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C8[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_16_0/COUT</td>
</tr>
<tr>
<td>8.390</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C9[0][A]</td>
<td>un3_cnt_cry_17_0/CIN</td>
</tr>
<tr>
<td>8.953</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C9[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_17_0/SUM</td>
</tr>
<tr>
<td>8.953</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C9[0][A]</td>
<td style=" font-weight:bold;">\cnt_Z[17] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C9[0][A]</td>
<td>\cnt_Z[17] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[17] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C9[0][A]</td>
<td>\cnt_Z[17] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>12</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.178, 47.521%; route: 1.947, 42.479%; tC2Q: 0.458, 10.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.931</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.839</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[6] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[15] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>\cnt_Z[6] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C12[0][A]</td>
<td style=" font-weight:bold;">\cnt_Z[6] /Q</td>
</tr>
<tr>
<td>6.775</td>
<td>1.947</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.820</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.820</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>7.877</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/COUT</td>
</tr>
<tr>
<td>7.877</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[1][B]</td>
<td>un3_cnt_cry_8_0/CIN</td>
</tr>
<tr>
<td>7.934</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/COUT</td>
</tr>
<tr>
<td>7.934</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[2][A]</td>
<td>un3_cnt_cry_9_0/CIN</td>
</tr>
<tr>
<td>7.991</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_9_0/COUT</td>
</tr>
<tr>
<td>7.991</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[2][B]</td>
<td>un3_cnt_cry_10_0/CIN</td>
</tr>
<tr>
<td>8.048</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_10_0/COUT</td>
</tr>
<tr>
<td>8.048</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C8[0][A]</td>
<td>un3_cnt_cry_11_0/CIN</td>
</tr>
<tr>
<td>8.105</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C8[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_11_0/COUT</td>
</tr>
<tr>
<td>8.105</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C8[0][B]</td>
<td>un3_cnt_cry_12_0/CIN</td>
</tr>
<tr>
<td>8.162</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C8[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_12_0/COUT</td>
</tr>
<tr>
<td>8.162</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C8[1][A]</td>
<td>un3_cnt_cry_13_0/CIN</td>
</tr>
<tr>
<td>8.219</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C8[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_13_0/COUT</td>
</tr>
<tr>
<td>8.219</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C8[1][B]</td>
<td>un3_cnt_cry_14_0/CIN</td>
</tr>
<tr>
<td>8.276</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C8[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_14_0/COUT</td>
</tr>
<tr>
<td>8.276</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C8[2][A]</td>
<td>un3_cnt_cry_15_0/CIN</td>
</tr>
<tr>
<td>8.839</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C8[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_15_0/SUM</td>
</tr>
<tr>
<td>8.839</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C8[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[15] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C8[2][A]</td>
<td>\cnt_Z[15] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[15] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C8[2][A]</td>
<td>\cnt_Z[15] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>10</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.064, 46.183%; route: 1.947, 43.562%; tC2Q: 0.458, 10.255%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.216</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.554</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[6] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[10] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>\cnt_Z[6] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C12[0][A]</td>
<td style=" font-weight:bold;">\cnt_Z[6] /Q</td>
</tr>
<tr>
<td>6.775</td>
<td>1.947</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.820</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.820</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>7.877</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/COUT</td>
</tr>
<tr>
<td>7.877</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[1][B]</td>
<td>un3_cnt_cry_8_0/CIN</td>
</tr>
<tr>
<td>7.934</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/COUT</td>
</tr>
<tr>
<td>7.934</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[2][A]</td>
<td>un3_cnt_cry_9_0/CIN</td>
</tr>
<tr>
<td>7.991</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_9_0/COUT</td>
</tr>
<tr>
<td>7.991</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[2][B]</td>
<td>un3_cnt_cry_10_0/CIN</td>
</tr>
<tr>
<td>8.554</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_10_0/SUM</td>
</tr>
<tr>
<td>8.554</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C7[2][B]</td>
<td style=" font-weight:bold;">\cnt_Z[10] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C7[2][B]</td>
<td>\cnt_Z[10] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[10] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C7[2][B]</td>
<td>\cnt_Z[10] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.779, 42.517%; route: 1.947, 46.529%; tC2Q: 0.458, 10.954%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.273</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.497</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[6] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[9] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>\cnt_Z[6] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C12[0][A]</td>
<td style=" font-weight:bold;">\cnt_Z[6] /Q</td>
</tr>
<tr>
<td>6.775</td>
<td>1.947</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.820</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.820</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>7.877</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/COUT</td>
</tr>
<tr>
<td>7.877</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[1][B]</td>
<td>un3_cnt_cry_8_0/CIN</td>
</tr>
<tr>
<td>7.934</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/COUT</td>
</tr>
<tr>
<td>7.934</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[2][A]</td>
<td>un3_cnt_cry_9_0/CIN</td>
</tr>
<tr>
<td>8.497</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_9_0/SUM</td>
</tr>
<tr>
<td>8.497</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C7[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[9] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C7[2][A]</td>
<td>\cnt_Z[9] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[9] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C7[2][A]</td>
<td>\cnt_Z[9] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.722, 41.723%; route: 1.947, 47.172%; tC2Q: 0.458, 11.105%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.330</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.440</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[6] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[8] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>\cnt_Z[6] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C12[0][A]</td>
<td style=" font-weight:bold;">\cnt_Z[6] /Q</td>
</tr>
<tr>
<td>6.775</td>
<td>1.947</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.820</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.820</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>7.877</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/COUT</td>
</tr>
<tr>
<td>7.877</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[1][B]</td>
<td>un3_cnt_cry_8_0/CIN</td>
</tr>
<tr>
<td>8.440</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/SUM</td>
</tr>
<tr>
<td>8.440</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C7[1][B]</td>
<td style=" font-weight:bold;">\cnt_Z[8] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C7[1][B]</td>
<td>\cnt_Z[8] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[8] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C7[1][B]</td>
<td>\cnt_Z[8] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.665, 40.907%; route: 1.947, 47.832%; tC2Q: 0.458, 11.261%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.387</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.383</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[6] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[7] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>\cnt_Z[6] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C12[0][A]</td>
<td style=" font-weight:bold;">\cnt_Z[6] /Q</td>
</tr>
<tr>
<td>6.775</td>
<td>1.947</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.820</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.820</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>8.383</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/SUM</td>
</tr>
<tr>
<td>8.383</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C7[1][A]</td>
<td style=" font-weight:bold;">\cnt_Z[7] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C7[1][A]</td>
<td>\cnt_Z[7] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[7] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C7[1][A]</td>
<td>\cnt_Z[7] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.608, 40.068%; route: 1.947, 48.512%; tC2Q: 0.458, 11.421%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.824</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.946</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[1] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[5] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[1][A]</td>
<td>\cnt_Z[1] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R11C6[1][A]</td>
<td style=" font-weight:bold;">\cnt_Z[1] /Q</td>
</tr>
<tr>
<td>5.167</td>
<td>0.339</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C6[1][A]</td>
<td>un3_cnt_cry_1_0/I0</td>
</tr>
<tr>
<td>6.212</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C6[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_1_0/COUT</td>
</tr>
<tr>
<td>6.212</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C6[1][B]</td>
<td>un3_cnt_cry_2_0/CIN</td>
</tr>
<tr>
<td>6.269</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C6[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_2_0/COUT</td>
</tr>
<tr>
<td>6.269</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C6[2][A]</td>
<td>un3_cnt_cry_3_0/CIN</td>
</tr>
<tr>
<td>6.326</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C6[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_3_0/COUT</td>
</tr>
<tr>
<td>6.326</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C6[2][B]</td>
<td>un3_cnt_cry_4_0/CIN</td>
</tr>
<tr>
<td>6.383</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C6[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_4_0/COUT</td>
</tr>
<tr>
<td>6.383</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[0][A]</td>
<td>un3_cnt_cry_5_0/CIN</td>
</tr>
<tr>
<td>6.946</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_5_0/SUM</td>
</tr>
<tr>
<td>6.946</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C7[0][A]</td>
<td style=" font-weight:bold;">\cnt_Z[5] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C7[0][A]</td>
<td>\cnt_Z[5] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[5] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C7[0][A]</td>
<td>\cnt_Z[5] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.779, 69.051%; route: 0.339, 13.158%; tC2Q: 0.458, 17.790%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.881</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.889</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[1] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[4] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[1][A]</td>
<td>\cnt_Z[1] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R11C6[1][A]</td>
<td style=" font-weight:bold;">\cnt_Z[1] /Q</td>
</tr>
<tr>
<td>5.167</td>
<td>0.339</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C6[1][A]</td>
<td>un3_cnt_cry_1_0/I0</td>
</tr>
<tr>
<td>6.212</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C6[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_1_0/COUT</td>
</tr>
<tr>
<td>6.212</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C6[1][B]</td>
<td>un3_cnt_cry_2_0/CIN</td>
</tr>
<tr>
<td>6.269</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C6[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_2_0/COUT</td>
</tr>
<tr>
<td>6.269</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C6[2][A]</td>
<td>un3_cnt_cry_3_0/CIN</td>
</tr>
<tr>
<td>6.326</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C6[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_3_0/COUT</td>
</tr>
<tr>
<td>6.326</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C6[2][B]</td>
<td>un3_cnt_cry_4_0/CIN</td>
</tr>
<tr>
<td>6.889</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C6[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_4_0/SUM</td>
</tr>
<tr>
<td>6.889</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C6[2][B]</td>
<td style=" font-weight:bold;">\cnt_Z[4] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[2][B]</td>
<td>\cnt_Z[4] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[4] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C6[2][B]</td>
<td>\cnt_Z[4] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.722, 68.351%; route: 0.339, 13.456%; tC2Q: 0.458, 18.193%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.938</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.832</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[1] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[3] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[1][A]</td>
<td>\cnt_Z[1] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R11C6[1][A]</td>
<td style=" font-weight:bold;">\cnt_Z[1] /Q</td>
</tr>
<tr>
<td>5.167</td>
<td>0.339</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C6[1][A]</td>
<td>un3_cnt_cry_1_0/I0</td>
</tr>
<tr>
<td>6.212</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C6[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_1_0/COUT</td>
</tr>
<tr>
<td>6.212</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C6[1][B]</td>
<td>un3_cnt_cry_2_0/CIN</td>
</tr>
<tr>
<td>6.269</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C6[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_2_0/COUT</td>
</tr>
<tr>
<td>6.269</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C6[2][A]</td>
<td>un3_cnt_cry_3_0/CIN</td>
</tr>
<tr>
<td>6.832</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C6[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_3_0/SUM</td>
</tr>
<tr>
<td>6.832</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C6[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[3] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[2][A]</td>
<td>\cnt_Z[3] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[3] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C6[2][A]</td>
<td>\cnt_Z[3] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.665, 67.619%; route: 0.339, 13.768%; tC2Q: 0.458, 18.614%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.995</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.775</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[1] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[2] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[1][A]</td>
<td>\cnt_Z[1] /CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R11C6[1][A]</td>
<td style=" font-weight:bold;">\cnt_Z[1] /Q</td>
</tr>
<tr>
<td>5.167</td>
<td>0.339</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C6[1][A]</td>
<td>un3_cnt_cry_1_0/I0</td>
</tr>
<tr>
<td>6.212</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C6[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_1_0/COUT</td>
</tr>
<tr>
<td>6.212</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C6[1][B]</td>
<td>un3_cnt_cry_2_0/CIN</td>
</tr>
<tr>
<td>6.775</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C6[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_2_0/SUM</td>
</tr>
<tr>
<td>6.775</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C6[1][B]</td>
<td style=" font-weight:bold;">\cnt_Z[2] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[1][B]</td>
<td>\cnt_Z[2] /CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[2] </td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C6[1][B]</td>
<td>\cnt_Z[2] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.608, 66.851%; route: 0.339, 14.094%; tC2Q: 0.458, 19.055%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.067</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_led_Z</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_led_Z</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C9[0][A]</td>
<td>clk_led_Z/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R12C9[0][A]</td>
<td style=" font-weight:bold;">clk_led_Z/Q</td>
</tr>
<tr>
<td>3.695</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C9[0][A]</td>
<td>clk_led_i_i_cZ/I0</td>
</tr>
<tr>
<td>4.067</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R12C9[0][A]</td>
<td style=" background: #97FFFF;">clk_led_i_i_cZ/F</td>
</tr>
<tr>
<td>4.067</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C9[0][A]</td>
<td style=" font-weight:bold;">clk_led_Z/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C9[0][A]</td>
<td>clk_led_Z/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>clk_led_Z</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R12C9[0][A]</td>
<td>clk_led_Z</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.853</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.212</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[8] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[8] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C7[1][B]</td>
<td>\cnt_Z[8] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R11C7[1][B]</td>
<td style=" font-weight:bold;">\cnt_Z[8] /Q</td>
</tr>
<tr>
<td>3.695</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C7[1][B]</td>
<td>un3_cnt_cry_8_0/I0</td>
</tr>
<tr>
<td>4.212</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R11C7[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/SUM</td>
</tr>
<tr>
<td>4.212</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C7[1][B]</td>
<td style=" font-weight:bold;">\cnt_Z[8] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C7[1][B]</td>
<td>\cnt_Z[8] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[8] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C7[1][B]</td>
<td>\cnt_Z[8] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.853</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.212</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[0] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[0] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[0][B]</td>
<td>\cnt_Z[0] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R11C6[0][B]</td>
<td style=" font-weight:bold;">\cnt_Z[0] /Q</td>
</tr>
<tr>
<td>3.695</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C6[0][B]</td>
<td>un3_cnt_cry_0_0/I0</td>
</tr>
<tr>
<td>4.212</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R11C6[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_0_0/SUM</td>
</tr>
<tr>
<td>4.212</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C6[0][B]</td>
<td style=" font-weight:bold;">\cnt_Z[0] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[0][B]</td>
<td>\cnt_Z[0] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[0] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C6[0][B]</td>
<td>\cnt_Z[0] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.853</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.212</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[2] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[2] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[1][B]</td>
<td>\cnt_Z[2] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R11C6[1][B]</td>
<td style=" font-weight:bold;">\cnt_Z[2] /Q</td>
</tr>
<tr>
<td>3.695</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C6[1][B]</td>
<td>un3_cnt_cry_2_0/I0</td>
</tr>
<tr>
<td>4.212</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R11C6[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_2_0/SUM</td>
</tr>
<tr>
<td>4.212</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C6[1][B]</td>
<td style=" font-weight:bold;">\cnt_Z[2] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[1][B]</td>
<td>\cnt_Z[2] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[2] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C6[1][B]</td>
<td>\cnt_Z[2] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.085</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.444</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[23] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[23] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C10[0][A]</td>
<td>\cnt_Z[23] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R11C10[0][A]</td>
<td style=" font-weight:bold;">\cnt_Z[23] /Q</td>
</tr>
<tr>
<td>3.927</td>
<td>0.234</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C10[0][A]</td>
<td>un3_cnt_cry_23_0/I0</td>
</tr>
<tr>
<td>4.444</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C10[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_23_0/SUM</td>
</tr>
<tr>
<td>4.444</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C10[0][A]</td>
<td style=" font-weight:bold;">\cnt_Z[23] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C10[0][A]</td>
<td>\cnt_Z[23] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[23] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C10[0][A]</td>
<td>\cnt_Z[23] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.658%; route: 0.234, 21.615%; tC2Q: 0.333, 30.727%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.085</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.444</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[10] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[10] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C7[2][B]</td>
<td>\cnt_Z[10] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R11C7[2][B]</td>
<td style=" font-weight:bold;">\cnt_Z[10] /Q</td>
</tr>
<tr>
<td>3.927</td>
<td>0.234</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[2][B]</td>
<td>un3_cnt_cry_10_0/I0</td>
</tr>
<tr>
<td>4.444</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_10_0/SUM</td>
</tr>
<tr>
<td>4.444</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C7[2][B]</td>
<td style=" font-weight:bold;">\cnt_Z[10] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C7[2][B]</td>
<td>\cnt_Z[10] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[10] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C7[2][B]</td>
<td>\cnt_Z[10] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.658%; route: 0.234, 21.615%; tC2Q: 0.333, 30.727%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.085</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.444</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[17] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[17] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C9[0][A]</td>
<td>\cnt_Z[17] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R11C9[0][A]</td>
<td style=" font-weight:bold;">\cnt_Z[17] /Q</td>
</tr>
<tr>
<td>3.927</td>
<td>0.234</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C9[0][A]</td>
<td>un3_cnt_cry_17_0/I0</td>
</tr>
<tr>
<td>4.444</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C9[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_17_0/SUM</td>
</tr>
<tr>
<td>4.444</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C9[0][A]</td>
<td style=" font-weight:bold;">\cnt_Z[17] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C9[0][A]</td>
<td>\cnt_Z[17] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[17] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C9[0][A]</td>
<td>\cnt_Z[17] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.658%; route: 0.234, 21.615%; tC2Q: 0.333, 30.727%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.085</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.444</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[4] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[4] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[2][B]</td>
<td>\cnt_Z[4] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R11C6[2][B]</td>
<td style=" font-weight:bold;">\cnt_Z[4] /Q</td>
</tr>
<tr>
<td>3.927</td>
<td>0.234</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C6[2][B]</td>
<td>un3_cnt_cry_4_0/I0</td>
</tr>
<tr>
<td>4.444</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C6[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_4_0/SUM</td>
</tr>
<tr>
<td>4.444</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C6[2][B]</td>
<td style=" font-weight:bold;">\cnt_Z[4] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[2][B]</td>
<td>\cnt_Z[4] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[4] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C6[2][B]</td>
<td>\cnt_Z[4] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.658%; route: 0.234, 21.615%; tC2Q: 0.333, 30.727%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.085</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.444</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[5] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[5] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C7[0][A]</td>
<td>\cnt_Z[5] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R11C7[0][A]</td>
<td style=" font-weight:bold;">\cnt_Z[5] /Q</td>
</tr>
<tr>
<td>3.927</td>
<td>0.234</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R11C7[0][A]</td>
<td>un3_cnt_cry_5_0/I0</td>
</tr>
<tr>
<td>4.444</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C7[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_5_0/SUM</td>
</tr>
<tr>
<td>4.444</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C7[0][A]</td>
<td style=" font-weight:bold;">\cnt_Z[5] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C7[0][A]</td>
<td>\cnt_Z[5] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[5] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C7[0][A]</td>
<td>\cnt_Z[5] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.658%; route: 0.234, 21.615%; tC2Q: 0.333, 30.727%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.088</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.447</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[9] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[9] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C7[2][A]</td>
<td>\cnt_Z[9] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R11C7[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[9] /Q</td>
</tr>
<tr>
<td>3.930</td>
<td>0.238</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C7[2][A]</td>
<td>un3_cnt_cry_9_0/I0</td>
</tr>
<tr>
<td>4.447</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R11C7[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_9_0/SUM</td>
</tr>
<tr>
<td>4.447</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C7[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[9] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C7[2][A]</td>
<td>\cnt_Z[9] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[9] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C7[2][A]</td>
<td>\cnt_Z[9] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.522%; route: 0.238, 21.838%; tC2Q: 0.333, 30.640%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.088</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.447</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[1] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[1] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[1][A]</td>
<td>\cnt_Z[1] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R11C6[1][A]</td>
<td style=" font-weight:bold;">\cnt_Z[1] /Q</td>
</tr>
<tr>
<td>3.930</td>
<td>0.238</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C6[1][A]</td>
<td>un3_cnt_cry_1_0/I0</td>
</tr>
<tr>
<td>4.447</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R11C6[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_1_0/SUM</td>
</tr>
<tr>
<td>4.447</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C6[1][A]</td>
<td style=" font-weight:bold;">\cnt_Z[1] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[1][A]</td>
<td>\cnt_Z[1] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[1] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C6[1][A]</td>
<td>\cnt_Z[1] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.522%; route: 0.238, 21.838%; tC2Q: 0.333, 30.640%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.093</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.452</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[7] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[7] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C7[1][A]</td>
<td>\cnt_Z[7] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R11C7[1][A]</td>
<td style=" font-weight:bold;">\cnt_Z[7] /Q</td>
</tr>
<tr>
<td>3.935</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C7[1][A]</td>
<td>un3_cnt_cry_7_0/I0</td>
</tr>
<tr>
<td>4.452</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R11C7[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/SUM</td>
</tr>
<tr>
<td>4.452</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C7[1][A]</td>
<td style=" font-weight:bold;">\cnt_Z[7] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C7[1][A]</td>
<td>\cnt_Z[7] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[7] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C7[1][A]</td>
<td>\cnt_Z[7] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.304%; route: 0.243, 22.197%; tC2Q: 0.333, 30.499%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.093</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.452</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[15] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[15] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C8[2][A]</td>
<td>\cnt_Z[15] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R11C8[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[15] /Q</td>
</tr>
<tr>
<td>3.935</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C8[2][A]</td>
<td>un3_cnt_cry_15_0/I0</td>
</tr>
<tr>
<td>4.452</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R11C8[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_15_0/SUM</td>
</tr>
<tr>
<td>4.452</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C8[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[15] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C8[2][A]</td>
<td>\cnt_Z[15] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[15] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C8[2][A]</td>
<td>\cnt_Z[15] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.304%; route: 0.243, 22.197%; tC2Q: 0.333, 30.499%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.093</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.452</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[3] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[3] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[2][A]</td>
<td>\cnt_Z[3] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R11C6[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[3] /Q</td>
</tr>
<tr>
<td>3.935</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C6[2][A]</td>
<td>un3_cnt_cry_3_0/I0</td>
</tr>
<tr>
<td>4.452</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R11C6[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_3_0/SUM</td>
</tr>
<tr>
<td>4.452</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C6[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[3] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[2][A]</td>
<td>\cnt_Z[3] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[3] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C6[2][A]</td>
<td>\cnt_Z[3] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.304%; route: 0.243, 22.197%; tC2Q: 0.333, 30.499%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.079</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.367</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.445</td>
</tr>
<tr>
<td class="label">From</td>
<td>\u_ao_top/u_ao_mem_ctrl/mem_mem_0_0 </td>
</tr>
<tr>
<td class="label">To</td>
<td>\u_ao_top/u_ao_mem_ctrl/mem_mem_0_0 </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.367</td>
<td>2.522</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[0]</td>
<td style=" font-weight:bold;">\u_ao_top/u_ao_mem_ctrl/mem_mem_0_0 /DI4</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[0]</td>
<td>\u_ao_top/u_ao_mem_ctrl/mem_mem_0_0 /CLKA</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\u_ao_top/u_ao_mem_ctrl/mem_mem_0_0 </td>
</tr>
<tr>
<td>3.445</td>
<td>0.086</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R10[0]</td>
<td>\u_ao_top/u_ao_mem_ctrl/mem_mem_0_0 </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.515</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>0</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 100.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 2.522, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.486</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.846</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[21] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[21] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[1][B]</td>
<td>\cnt_Z[21] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R9C11[1][B]</td>
<td style=" font-weight:bold;">\cnt_Z[21] /Q</td>
</tr>
<tr>
<td>4.223</td>
<td>0.530</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C9[2][A]</td>
<td>un3_cnt_cry_21_0/I0</td>
</tr>
<tr>
<td>4.761</td>
<td>0.538</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C9[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_21_0/SUM</td>
</tr>
<tr>
<td>5.290</td>
<td>0.529</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[1][B]</td>
<td>\cnt_3_cZ[21] /I0</td>
</tr>
<tr>
<td>5.846</td>
<td>0.556</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C11[1][B]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[21] /F</td>
</tr>
<tr>
<td>5.846</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[1][B]</td>
<td style=" font-weight:bold;">\cnt_Z[21] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[1][B]</td>
<td>\cnt_Z[21] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[21] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C11[1][B]</td>
<td>\cnt_Z[21] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.094, 44.001%; route: 1.059, 42.592%; tC2Q: 0.333, 13.407%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.565</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.924</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[24] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[24] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][B]</td>
<td>\cnt_Z[24] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R9C11[2][B]</td>
<td style=" font-weight:bold;">\cnt_Z[24] /Q</td>
</tr>
<tr>
<td>4.264</td>
<td>0.572</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C10[0][B]</td>
<td>un3_cnt_s_24_0/I0</td>
</tr>
<tr>
<td>4.781</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R11C10[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_s_24_0/SUM</td>
</tr>
<tr>
<td>5.368</td>
<td>0.587</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C11[2][B]</td>
<td>\cnt_3_cZ[24] /I0</td>
</tr>
<tr>
<td>5.924</td>
<td>0.556</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R9C11[2][B]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[24] /F</td>
</tr>
<tr>
<td>5.924</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][B]</td>
<td style=" font-weight:bold;">\cnt_Z[24] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][B]</td>
<td>\cnt_Z[24] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[24] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C11[2][B]</td>
<td>\cnt_Z[24] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.073, 41.832%; route: 1.159, 45.172%; tC2Q: 0.333, 12.995%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.608</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.967</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[19] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[19] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[0][A]</td>
<td>\cnt_Z[19] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R9C11[0][A]</td>
<td style=" font-weight:bold;">\cnt_Z[19] /Q</td>
</tr>
<tr>
<td>4.528</td>
<td>0.835</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C9[1][A]</td>
<td>un3_cnt_cry_19_0/I0</td>
</tr>
<tr>
<td>5.066</td>
<td>0.538</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C9[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_19_0/SUM</td>
</tr>
<tr>
<td>5.595</td>
<td>0.529</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[0][A]</td>
<td>\cnt_3_cZ[19] /I0</td>
</tr>
<tr>
<td>5.967</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C11[0][A]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[19] /F</td>
</tr>
<tr>
<td>5.967</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C11[0][A]</td>
<td style=" font-weight:bold;">\cnt_Z[19] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[0][A]</td>
<td>\cnt_Z[19] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[19] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C11[0][A]</td>
<td>\cnt_Z[19] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.910, 34.896%; route: 1.364, 52.321%; tC2Q: 0.333, 12.782%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.657</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.016</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[18] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[18] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[0][B]</td>
<td>\cnt_Z[18] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R9C11[0][B]</td>
<td style=" font-weight:bold;">\cnt_Z[18] /Q</td>
</tr>
<tr>
<td>4.225</td>
<td>0.532</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C9[0][B]</td>
<td>un3_cnt_cry_18_0/I0</td>
</tr>
<tr>
<td>4.763</td>
<td>0.538</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C9[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_18_0/SUM</td>
</tr>
<tr>
<td>5.292</td>
<td>0.529</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[0][B]</td>
<td>\cnt_3_cZ[18] /I0</td>
</tr>
<tr>
<td>6.016</td>
<td>0.724</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C11[0][B]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[18] /F</td>
</tr>
<tr>
<td>6.016</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[0][B]</td>
<td style=" font-weight:bold;">\cnt_Z[18] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[0][B]</td>
<td>\cnt_Z[18] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[18] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C11[0][B]</td>
<td>\cnt_Z[18] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.262, 47.500%; route: 1.062, 39.954%; tC2Q: 0.333, 12.546%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.692</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.052</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[13] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[13] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[1][B]</td>
<td>\cnt_Z[13] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R9C12[1][B]</td>
<td style=" font-weight:bold;">\cnt_Z[13] /Q</td>
</tr>
<tr>
<td>4.242</td>
<td>0.549</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C8[1][A]</td>
<td>un3_cnt_cry_13_0/I0</td>
</tr>
<tr>
<td>4.780</td>
<td>0.538</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C8[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_13_0/SUM</td>
</tr>
<tr>
<td>5.328</td>
<td>0.548</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[1][B]</td>
<td>\cnt_3_cZ[13] /I0</td>
</tr>
<tr>
<td>6.052</td>
<td>0.724</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C12[1][B]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[13] /F</td>
</tr>
<tr>
<td>6.052</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[1][B]</td>
<td style=" font-weight:bold;">\cnt_Z[13] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[1][B]</td>
<td>\cnt_Z[13] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[13] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C12[1][B]</td>
<td>\cnt_Z[13] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.262, 46.872%; route: 1.097, 40.747%; tC2Q: 0.333, 12.380%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.751</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.110</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[8] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[14] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C7[1][B]</td>
<td>\cnt_Z[8] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R11C7[1][B]</td>
<td style=" font-weight:bold;">\cnt_Z[8] /Q</td>
</tr>
<tr>
<td>3.695</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C7[1][B]</td>
<td>un3_cnt_cry_8_0/I0</td>
</tr>
<tr>
<td>4.369</td>
<td>0.674</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C7[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/COUT</td>
</tr>
<tr>
<td>4.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C7[2][A]</td>
<td>un3_cnt_cry_9_0/CIN</td>
</tr>
<tr>
<td>4.400</td>
<td>0.031</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C7[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_9_0/COUT</td>
</tr>
<tr>
<td>4.400</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C7[2][B]</td>
<td>un3_cnt_cry_10_0/CIN</td>
</tr>
<tr>
<td>4.431</td>
<td>0.031</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C7[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_10_0/COUT</td>
</tr>
<tr>
<td>4.431</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C8[0][A]</td>
<td>un3_cnt_cry_11_0/CIN</td>
</tr>
<tr>
<td>4.462</td>
<td>0.031</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C8[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_11_0/COUT</td>
</tr>
<tr>
<td>4.462</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C8[0][B]</td>
<td>un3_cnt_cry_12_0/CIN</td>
</tr>
<tr>
<td>4.493</td>
<td>0.031</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C8[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_12_0/COUT</td>
</tr>
<tr>
<td>4.493</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C8[1][A]</td>
<td>un3_cnt_cry_13_0/CIN</td>
</tr>
<tr>
<td>4.524</td>
<td>0.031</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C8[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_13_0/COUT</td>
</tr>
<tr>
<td>4.524</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C8[1][B]</td>
<td>un3_cnt_cry_14_0/CIN</td>
</tr>
<tr>
<td>5.006</td>
<td>0.482</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C8[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_14_0/SUM</td>
</tr>
<tr>
<td>5.554</td>
<td>0.548</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[2][B]</td>
<td>\cnt_3_cZ[14] /I0</td>
</tr>
<tr>
<td>6.110</td>
<td>0.556</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C12[2][B]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[14] /F</td>
</tr>
<tr>
<td>6.110</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[2][B]</td>
<td style=" font-weight:bold;">\cnt_Z[14] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[2][B]</td>
<td>\cnt_Z[14] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[14] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C12[2][B]</td>
<td>\cnt_Z[14] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.867, 67.870%; route: 0.551, 20.013%; tC2Q: 0.333, 12.117%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.889</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.249</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[22] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[22] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>\cnt_Z[22] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R9C11[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[22] /Q</td>
</tr>
<tr>
<td>4.458</td>
<td>0.765</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C9[2][B]</td>
<td>un3_cnt_cry_22_0/I0</td>
</tr>
<tr>
<td>4.996</td>
<td>0.538</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C9[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_22_0/SUM</td>
</tr>
<tr>
<td>5.525</td>
<td>0.529</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>\cnt_3_cZ[22] /I0</td>
</tr>
<tr>
<td>6.249</td>
<td>0.724</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[22] /F</td>
</tr>
<tr>
<td>6.249</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[22] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>\cnt_Z[22] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[22] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>\cnt_Z[22] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.262, 43.675%; route: 1.294, 44.788%; tC2Q: 0.333, 11.536%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.892</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.251</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[20] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[20] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[1][A]</td>
<td>\cnt_Z[20] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R9C11[1][A]</td>
<td style=" font-weight:bold;">\cnt_Z[20] /Q</td>
</tr>
<tr>
<td>4.460</td>
<td>0.768</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C9[1][B]</td>
<td>un3_cnt_cry_20_0/I0</td>
</tr>
<tr>
<td>4.998</td>
<td>0.538</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C9[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_20_0/SUM</td>
</tr>
<tr>
<td>5.527</td>
<td>0.529</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[1][A]</td>
<td>\cnt_3_cZ[20] /I0</td>
</tr>
<tr>
<td>6.251</td>
<td>0.724</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C11[1][A]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[20] /F</td>
</tr>
<tr>
<td>6.251</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[1][A]</td>
<td style=" font-weight:bold;">\cnt_Z[20] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[1][A]</td>
<td>\cnt_Z[20] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[20] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C11[1][A]</td>
<td>\cnt_Z[20] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.262, 43.637%; route: 1.297, 44.838%; tC2Q: 0.333, 11.526%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.939</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.298</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[16] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[16] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[2][A]</td>
<td>\cnt_Z[16] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R9C12[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[16] /Q</td>
</tr>
<tr>
<td>4.242</td>
<td>0.549</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C8[2][B]</td>
<td>un3_cnt_cry_16_0/I0</td>
</tr>
<tr>
<td>4.780</td>
<td>0.538</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C8[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_16_0/SUM</td>
</tr>
<tr>
<td>5.572</td>
<td>0.793</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[2][A]</td>
<td>\cnt_3_cZ[16] /I0</td>
</tr>
<tr>
<td>6.298</td>
<td>0.726</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C12[2][A]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[16] /F</td>
</tr>
<tr>
<td>6.298</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[2][A]</td>
<td style=" font-weight:bold;">\cnt_Z[16] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[2][A]</td>
<td>\cnt_Z[16] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[16] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C12[2][A]</td>
<td>\cnt_Z[16] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.264, 43.006%; route: 1.342, 45.652%; tC2Q: 0.333, 11.341%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.994</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.354</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>\cnt_Z[2] </td>
</tr>
<tr>
<td class="label">To</td>
<td>\cnt_Z[6] </td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[1][B]</td>
<td>\cnt_Z[2] /CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R11C6[1][B]</td>
<td style=" font-weight:bold;">\cnt_Z[2] /Q</td>
</tr>
<tr>
<td>3.695</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C6[1][B]</td>
<td>un3_cnt_cry_2_0/I0</td>
</tr>
<tr>
<td>4.369</td>
<td>0.674</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C6[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_2_0/COUT</td>
</tr>
<tr>
<td>4.369</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C6[2][A]</td>
<td>un3_cnt_cry_3_0/CIN</td>
</tr>
<tr>
<td>4.400</td>
<td>0.031</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C6[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_3_0/COUT</td>
</tr>
<tr>
<td>4.400</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C6[2][B]</td>
<td>un3_cnt_cry_4_0/CIN</td>
</tr>
<tr>
<td>4.431</td>
<td>0.031</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C6[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_4_0/COUT</td>
</tr>
<tr>
<td>4.431</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C7[0][A]</td>
<td>un3_cnt_cry_5_0/CIN</td>
</tr>
<tr>
<td>4.462</td>
<td>0.031</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C7[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_5_0/COUT</td>
</tr>
<tr>
<td>4.462</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R11C7[0][B]</td>
<td>un3_cnt_cry_6_0/CIN</td>
</tr>
<tr>
<td>4.944</td>
<td>0.482</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C7[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/SUM</td>
</tr>
<tr>
<td>5.798</td>
<td>0.854</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>\cnt_3_cZ[6] /I0</td>
</tr>
<tr>
<td>6.354</td>
<td>0.556</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td style=" background: #97FFFF;">\cnt_3_cZ[6] /F</td>
</tr>
<tr>
<td>6.354</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td style=" font-weight:bold;">\cnt_Z[6] /D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>74</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>\cnt_Z[6] /CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>\cnt_Z[6] </td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>\cnt_Z[6] </td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.805, 60.281%; route: 0.856, 28.587%; tC2Q: 0.333, 11.132%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>No recovery paths to report!</h4>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>No removal paths to report!</h4>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>\cnt_Z[5] </td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>\cnt_Z[5] /CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>\cnt_Z[5] /CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>\cnt_Z[3] </td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>\cnt_Z[3] /CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>\cnt_Z[3] /CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>\cnt_Z[20] </td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>\cnt_Z[20] /CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>\cnt_Z[20] /CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>\cnt_Z[12] </td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>\cnt_Z[12] /CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>\cnt_Z[12] /CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>\u_ao_top/internal_reg_start_dly_Z[0] </td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>\u_ao_top/internal_reg_start_dly_Z[0] /CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>\u_ao_top/internal_reg_start_dly_Z[0] /CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>\u_ao_top/internal_reg_start_dly_Z[1] </td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>\u_ao_top/internal_reg_start_dly_Z[1] /CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>\u_ao_top/internal_reg_start_dly_Z[1] /CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>\cnt_Z[13] </td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>\cnt_Z[13] /CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>\cnt_Z[13] /CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>\u_ao_top/rst_ao_Z </td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>\u_ao_top/rst_ao_Z /CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>\u_ao_top/rst_ao_Z /CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>\u_ao_top/rst_ao_syn_Z </td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>\u_ao_top/rst_ao_syn_Z /CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>\u_ao_top/rst_ao_syn_Z /CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>\cnt_Z[0] </td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>\cnt_Z[0] /CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>\cnt_Z[0] /CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>26</td>
<td>clk_50M_c</td>
<td>1.653</td>
<td>3.796</td>
</tr>
<tr>
<td>13</td>
<td>clk_led4</td>
<td>1.653</td>
<td>2.147</td>
</tr>
<tr>
<td>5</td>
<td>clk_led</td>
<td>8.307</td>
<td>1.856</td>
</tr>
<tr>
<td>2</td>
<td>cnt[7]</td>
<td>3.680</td>
<td>0.345</td>
</tr>
<tr>
<td>2</td>
<td>cnt[8]</td>
<td>4.091</td>
<td>0.339</td>
</tr>
<tr>
<td>2</td>
<td>cnt[24]</td>
<td>2.194</td>
<td>0.807</td>
</tr>
<tr>
<td>2</td>
<td>cnt[23]</td>
<td>2.728</td>
<td>0.824</td>
</tr>
<tr>
<td>2</td>
<td>cnt[21]</td>
<td>1.917</td>
<td>0.977</td>
</tr>
<tr>
<td>2</td>
<td>cnt[22]</td>
<td>1.653</td>
<td>1.308</td>
</tr>
<tr>
<td>2</td>
<td>cnt[20]</td>
<td>2.638</td>
<td>1.309</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R11C9</td>
<td>0.250</td>
</tr>
<tr>
<td>R9C11</td>
<td>0.222</td>
</tr>
<tr>
<td>R11C8</td>
<td>0.208</td>
</tr>
<tr>
<td>R9C12</td>
<td>0.181</td>
</tr>
<tr>
<td>R11C7</td>
<td>0.181</td>
</tr>
<tr>
<td>R11C6</td>
<td>0.167</td>
</tr>
<tr>
<td>R9C9</td>
<td>0.153</td>
</tr>
<tr>
<td>R12C16</td>
<td>0.139</td>
</tr>
<tr>
<td>R9C10</td>
<td>0.125</td>
</tr>
<tr>
<td>R11C10</td>
<td>0.125</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
</table>
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